Design and analysis of sense amplifiers for sub-threshold Static Random Access Memories

碩士 === 國立中正大學 === 電機工程研究所 === 99 === The sense amplifier is a key design in Static Random Access Memoey.It dominates the stability of read and power consumption when the random access memory is accessed. Therefore, lowering the operating voltage of Static Random Access Memory must also reduce the op...

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Bibliographic Details
Main Authors: Chen, Chun-Heng, 陳鈞恒
Other Authors: Wang, Jinn-Shyan
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/17218561191693154981
Description
Summary:碩士 === 國立中正大學 === 電機工程研究所 === 99 === The sense amplifier is a key design in Static Random Access Memoey.It dominates the stability of read and power consumption when the random access memory is accessed. Therefore, lowering the operating voltage of Static Random Access Memory must also reduce the operating voltage of sense amplifier at the same time to maintain the correctness of its reading. The trend of operating voltage of Static Random Access Memoey is more and more lower,even lower than threshold voltage called sub-threshold region. The sense amplifier has more and more challenges when it operates at sub-threshold region. Such as sensing margin lowering causes the decrease of reliability of reading. Leakage current relative to the high voltage becomes more severe. It makes function failures or speed down.So how to make low voltage sense amplifier for stable operation is a key point on research.When the process is more and more advanced, the process variance is also more and more serious. The main functions of the sense amplifier are to increase the speed and decreases bit line swing magnitude to reduce power consumption. To reduce power consumption of the sense amplifier, the traditional architectures use the enable line. By controling the timing of enable line, the sense amplifier evaluates when thevoltage of bit line is falled down enough. But process variance increase when the process goes into nanometer stage.The timing control of enable line also suffer form it,and the operating speed of Static Random Access Memoey decreases as well.If the process variation of Static Random Access Memoey cell and the timing variation of word-line are counted in, the operating speed of all must be impacted. This studty is for multiple low voltage sense amplifier relative improvement in the mechanism proposed to improve the overall stability, and proposed a new framework of sense amplifier and sense amplifier above its operating voltage set at times threshold voltage. Operating voltage drop represents the Static Random Access Memory power consumption also will decrease. because the consideration of the process, voltage, temperature variances, the traditional low-voltage sense amplifier may use buffer amplifier.Its drawbak is too slow that it makes overall performance down .Due the bit-line leakage is more serious at low voltage than at normal voltage,it makes buffer amplifier sensing wrong.First,for traditional low-voltage sense amplifier - buffer amplifier, design in its sub-threshold voltage, then it susceptible to leakage current effects of improved. Research topic is divided into two categories: first, Using self-adjusting dynamic trip ponit of the inverter can sense a drop due to leakage current and the bit line accessed due to the decline of the difference between bit line to complete the correct reading.Second,for the serious bit-line leakage at sub-threshold voltage,using the leakage detection mechanism and proposed sense amplifier. The mechanism is characterized with real-time correction function for different variance of the change in resistance and tolerance with a higher degree.