| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 99 === A research of radio frequency power detector for wideband operation is studied with a successive detection logarithmic amplifier (SDLA) topology and then we fabricate the related designs by TSMC 1P6M 0.18-μm. SDLA composes of limiting amplifier, unbalanced source-coupled differential pairs and low-pass filter. In order to increase the operating frequency, three types of limiting amplifiers will be analyzed. First, an active inductor topology is used to increase the 3-dB bandwidth of common source differential pair with body bias. The results show that the applicable frequency range reaches to 6 GHz with the overall dynamic range being more than 30 dB as, the logarithmic error within ± 1dB. The power consumption is 18.72-mW and chip size is 0.341-mm2. Second and third types are active feedback topology and PMOS loaded Cherry Hooper topology makes the operating frequency extended to 8 GHz with the overall dynamic range being more than 30 dB as the logarithmic error within ± 1dB. Second type takes 25.46-mW power consumption and 0.381-mm2 chip area. For the third one, power consumption is 18.72-mW and chip size is 0.341-mm2. By these ways, both the chip area and power consumption are effectively reduced.
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