| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 99 === Read Only Memories (ROMs) ,which have nonvolatile, high reliability, small area, high speed ,high compatible , are commonly embedded in SOCs to store lot of fixed programs and datum. In trend of mobile and multimedia systems on chip, a high capacity, low power, low voltage and high speed ROM is current trend for those applications. In order to shorten Turn Around Time in manufacturing after code modification to achieve fast time to market , Via(contact) and Metal Programming ROMs is popular in current design. Unfortunately, Via(contact) and Metal Programming ROMs which suffer Code-Pattern dependent bitline Loading, Crosstalk Noise, BL Leakage and PVT variations ,is hard to design for low voltage Chips.
This Study Proposes a dynamic segmentation shielding structure (DSS) to overcome Code-Pattern Induced bitline(BL) loading and Crosstalk problem , lower the leakage and leakage path, reduce BL loading to improve power consumption and speed without too many peripheral overhead and complicated code algorithm to achieve a low voltage high speed embedded ROM.
Experiment on a fabricated 256Kb macro using UMC 90nm 1P9M mixed-mode Logic CMOS process and validation is correct . Implement a low voltage , low power, high speed and full code coverage ROM.
|
|---|
