An Inter-frame/Inter-view Cache Architecture Design For Multi-view Video Decoder

• Main Authors: Wang, Sheng-Han, 王聲翰
• Other Authors: Guo,Jin-in
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/37304340502220091730

碩士 === 國立中正大學 === 資訊工程研究所 === 100 === This thesis presents a low-bandwidth two-level inter-frame/inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level inter-frame cache is developed for the single video decoder core, which is able to reduce 40% bandwidth in P frame and 60% in B frame in doing inter-frame prediction in average. Moreover, we develop the second level inter-view cache architecture to reuse the same reference data for doing inter-view prediction among different decoder cores, which can further reduce 30% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.