| Summary: | 碩士 === 元智大學 === 通訊工程學系 === 98 === The present paper is using TSMC 0.18μm CMOS process to design a receiver for UWB system. The present paper contains two actual manufactures to complete the electric circuit, one is 3.1~10.6GHz LNA other one is 3~5GHz VCO. In addition combine and design a receiver for 3.1~10.6GHz UWB system.
In order to reach goals such as the wide-band frequency, low power consumption, low noise figure and reduction chip size . The 3.1~10.6GHz LNA adopts the Current Reuse structure and used resistive feedback and Peaking inductor technology. The measurement results demonstrate the following performances of the design: The total power consumption is 14.4mW under 1.8V supply voltage, the forward gain is 9.7±1.1dB for 3.1~10.6 GHz wideband frequency, the noise figure is 3.4~3.84dB, and
the P1dB is -15~-10.5dBm. The chip area is 0.78mm*0.82mm.
The 3~5GHz VCO adopts the complementary cross-coupled structure and used switched inductance and switch Capacitor technology. The measurement demonstrate the following performances of the design: The total power consumption is 7.2~7.75mW under 1.2V supply voltage, the oscillation frequency ranges is situated between 2.77-4.6GHz, the output power ranges is situated between 0.2~2.81dBm, the phase noise is situated between -109.6 ~ -119dBc/Hz @1MHz, The chip area is
0.87mm*0.8mm.
The receiver for 3.1~10.6GHz UWB system, this circuit combines the UWB LNA in the thesis, and an active RF Balun of 2~11GHz, there are one mixer of 2~13GHz and an active IF Balun. The simulation results demonstrate the following performances of the design: The total power consumption is 33.9mW, the conversion gain is 38.8±0.9dB for 3.1~10.6 GHz wideband frequency, the noise figure is 7.36~7.73dB, and the IIP3 is -40.28dBm@7GHz. The chip area is 0.818mm*1.4mm.
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