Variable Step-size Adaptive Algorithms and Efficient Tap-selective FPGA Architecture for Channel Estimation Application

• Main Authors: Yuan-Ping Li, 李芫秤
• Other Authors: Jeng-Kuang Hwang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/04855374087950708559

博士 === 元智大學 === 電機工程學系 === 98 === In this dissertation, we first treat the problem of adaptive estimation of finite impulse response channel. Adaptive filter is a filter that can self-adjust its weight coefficients according to an optimizing algorithm, i.e., the adaptation algorithm. For practical application, the least-mean-square (LMS) algorithm is the most appealing and widely used adaptation algorithm, due to its simplicity and low complexity. However, it suffers from slow convergence and high excess mean-squared error (EMSE). In this dissertation, we investigate a family of variable step-size LMS (VSLMS) algorithms for application to channel estimation, and propose a new gradient-based VSLMS algorithm. It utilizes an average of the noisy gradient vector estimate to adjust the step-size, thus reducing the noise effect. As compared to a lot of existing VSLMS algorithms, the proposed algorithm has faster convergence rate and attains a lower EMSE under low-SNR environments. Second, an adaptive neural network cost function (ANNCF)-based VSLMS algorithm is proposed by exploiting an average of the modeling errors at two adjacent time instants. It also improves the convergence rate and MSE. Next, for block transmission system with cyclic prefix insertion, we consider a newly proposed low-complexity tap-selective maximum-likelihood (TSML) algorithm with the minimum description length (MDL) criterion. Via Xilinx FPGA platform and System Generator (SG) top-down design flow, architecture and modular hardware design of the above channel estimation algorithm is tackled. Especially, we consider the issue of implementing the natural logarithmic function (NLF) with a large input dynamic range. Finally, since the TSML algorithm requires only a few chosen channel taps to be computed, we address three efficient methods, namely, the SCPR-IDFT (Split-Coefficient Precomputed Recursive IDFT), SSOR-IDFT (Sliding Second-Order Recursive IDFT)，and SRSR-IDFT(Sliding Register-Split Recursive IDFT) method, with their associated hardware structures to improve the computational efficiency of the inverse fast Fourier transform (IFFT) in the TSML algorithm.