Test Data Compression for Scan-Based Designs
博士 === 元智大學 === 資訊工程學系 === 98 === A single-chip SOC design consists of a number of modules and intellectual property (IP) cores where a mass of transistors are used. Although increasing integration produces robust designs, many more faults are created accordingly. To detect them, a large amount of t...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20236635742550782954 |