Logic Synthesis for Hybrid LUT/SOP Reconfigurable Design Style
碩士 === 元智大學 === 資訊工程學系 === 98 === We propose a new hybrid FPGA architecture with both the SOP-cell and 4-input LUT to improve logic utilization of pure LUT and pure macro-cell architectures. The SOP-cell is composed of 5 NAND4 gates with smaller logic delay and transistor count as compared to LUT an...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76392191268112395986 |
| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 98 === We propose a new hybrid FPGA architecture with both the SOP-cell and 4-input LUT to improve logic utilization of pure LUT and pure macro-cell architectures. The SOP-cell is composed of 5 NAND4 gates with smaller logic delay and transistor count as compared to LUT and macro-cell. Furthermore, we propose a performance-driven logic synthesis design flow for our hybrid FPGA architecture. According to architectural evaluation results, we use two SOP-cells combined with one LUT as our hybrid configurable logic block. The experimental results indicate that our SOP-cell and synthesis technique achieve average 37.6% circuit delay reduction and average 51.01% transistor count reduction.
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