Programmable Clock Synthesizer based on Delay-Locked Loop

• Main Authors: Jyun-Hong Chen, 陳俊宏
• Other Authors: Chorng-Sii Hwang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/11669177599559781706

碩士 === 雲林科技大學 === 電機工程系碩士班 === 98 === With the rapid progress of the modern technology, Integrated Circuits (ICs) have become important parts of our lives. Since the transistor sizes of ICs are continuously shrinking with advanced manufacturing processes, high-speed clock synthesizers have more demand in the market. The common architectures of the clock synthesizers can be classified into two kinds. The first one is based on phase-locked loop (PLL); the other is with the aid of delay-locked loop (DLL). In this thesis, the proposed clock synthesizer is designed by using DLL according to its several inherent advantages like less jitter accumulation, fast-locking, the system stability, a first order system with a capacitor that can be easily to be integrated into the chip with small area ...etc. In the past, the well-known structures in the literature shows that DLL-based clock synthesizers can only provide multiplication ratios with the basic integers and a half factors (e.g. 6.5x, 7.5x ...) instead of achieving a greater variety of multiplication factors. Therefore, we propose a new architecture using DLL to provide the capability of fractional multiplication while sustaining the advantages of DLL. By adding a new circuit into the DLL-based clock generator, it can achieve a greater variety of fractional factors (8/3, 15/8 ...), up to 18 choices of multiplication factors in the scheme. The DLL-based clock synthesizer is designed and implemented with TSMC CMOS 0.18μm 1P6M process. The output frequency range of the proposed clock synthesizer is within 300MHz ~ 2.4GHz while the input frequency is 300MHz