A Compact Variable Node Using Thermalcode Addition Technique for Low Density Parity Check Decoder
碩士 === 雲林科技大學 === 電子與資訊工程研究所 === 98 === In the present error correction technology for digital data, Low-Density Parity-Check Code (LDPC) is with the bit-error-rate performance closest to Shannon limit. The earliest LDPC decoding algorithm is Sum-Product algorithm (SPA), which is mainly consisted of...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43822828865079165107 |