Architecture Design and FPGA Implementation of Layered Orthogonal Lattice Detector for Multiple-Input Multiple-Output Systems
碩士 === 雲林科技大學 === 電子與資訊工程研究所 === 98 === In recent years, with the increasing use of wireless communications in applications such as cell phone video and multimedia downloads, it requires more high-speed wireless communications. Multiple-input multiple-output (MIMO) systems have shown significant inc...
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| Format: | Others |
| Language: | zh-TW |
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2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82953887356280372815 |
| Summary: | 碩士 === 雲林科技大學 === 電子與資訊工程研究所 === 98 === In recent years, with the increasing use of wireless communications in applications such as cell phone video and multimedia downloads, it requires more high-speed wireless communications.
Multiple-input multiple-output (MIMO) systems have shown significant increase in spectral efficiency using arrays of transmit and receive antennas with spatial processing. The performance improvements resulting from MIMO systems come at the cost of increasing the computational complexity in the receiver for signal detection.
In this thesis, we present a novel MIMO signal detection circuit architecture and FPGA implementation based on Layered ORthogonal lattice Detector (LORD). LORD can approach near-ML performance with a fixed computational complexity. The thesis presents a reusable hardware and it works on 4 × 4 16 QAM MIMO system.
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