Design of a crosspoint queued router for a micro-network in SoCs
碩士 === 雲林科技大學 === 資訊工程研究所 === 98 === Due to the advancement of process technology for integrated circuits, more processes can be integrated into a System on Chip (SoC). It causes the challenge of communication aspect in a SoC. Therefore, the concept of Network on Chip (NoC) was proposed. Most resear...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/42836010586461298669 |
Similar Items
A Study of Test Schedule Optimization for Multicore SoCs
by: Wei-Che Cheng, et al.
Published: (2018)
by: Wei-Che Cheng, et al.
Published: (2018)