FPGA Implementation of the Twofish-256 Block Cipher and Related Application

• Main Authors: Quo-nan Lan, 藍國男
• Other Authors: Lih-Chyau Wuu
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/37749852584596066964

碩士 === 雲林科技大學 === 資訊工程研究所 === 98 === In the development of Internet communications, the issues of information security have been a very popular research scope. Symmetrical block cipher system－Twofish256, comparing with asymmetrical block cipher system, provides faster data encryption/decryption. The data length in each round of block cipher system increases from 128bits to 256bits, which enhances the difficulty for attackers to brute force attack. In addition to the advantages mentioned above, Twofish256 is easy to be implemented in hardware. In this thesis, we would like to implement the Twofish256 encryption/decryption cipher with an FPGA(Field Programmable Gate Array) manufactured by Altera Company. The method used in our design was hierarchically bottom-up. Moreover, the chip performed data encryption, decryption and key generation in a single hardware unit in order to save the chip area. In this thesis, the Twofish256 was implemented through the use of Hardware Description Language, the simulation with ModelSim, the compilation with Quartus II, and the use of FPGA Cyclone EP1C6 to verify the implementation. The design used 3740 LEs. This thesis further applied Twofish256 in OMAC(One-Key CBC MAC), in which we used Twofish256 block cipher system to implement a safe and efficient message authentication code mechanism called OMAC-Twofish256. The number of logic cell in OMAC-Twofish256 was 3914 LEs.