| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a switched-capacitor (SC) double-sampling three-bit sixth-order bandpass delta-sigma modulator with tunable resonators is proposed. It achieves sixth-order noise shaping by using tunable SC resonators and quantization noise coupling, and only three opamps are used so that the overall power consumption is lower compared to that of the conventional architecture. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. Besides, the tunable resonator can increase the signal-to-noise and distortion ratio (SNDR) in lower oversampling ratio situation by properly adjusting the resonator frequency. In addition, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. This adder is also used for quantization noise coupling to provide further noise shaping. Additionally, we present the filter-based data-weighted averaging (DWA) to modify the nonlinearity problem of the digital-to-analog converter generated by capacitor mismatch errors.
The design procedure is summarized in the following: First, we use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply, clock frequency is 40MHz (effective frequency would be 80MHz), and the input center frequency is 20MHz in TSMC 0.18?慆 CMOS 1P6M process. Simulation results reveal that the peak SNDR is 59.65 dB with -6dBFS input for bandwidth 2.5MHz (OSR=16), and power consumption is 39.28mW.
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