PARALLEL AND PIPELINE ARCHITECTURE-COMBINED FOR AES PROCESSER

• Main Authors: Wei-Zhong Wang, 王尉仲
• Other Authors: Ming-Chieh Tsai
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/44845150572080084362

碩士 === 大同大學 === 電機工程學系(所) === 98 === Most data transmit through the network are the form of pure document. These data were caught easily by other people. That leads some sensitive information to disclose. Encrypt is the key operation to insure data safety. AES algorithm is the process of data translates to code. It can protect data against intruder. Initially, most AES algorithms are implemented in software; however the software encryption could not follow the transmission speed. This leads to hardware design of AES where parallel processing and pipelining is possible. The hardware construction divides into parallel processing and pipeline processing roughly. The parallel processing suit to low circuit area, and the pipeline processing suit to high throughput. Thus, hardware systems offer superior throughput performance, but increase hardware area. We proposed a new pipeline FPGA implementation of AES algorithm based on the parallel architecture. In addition to, this thesis proposed a new ShiftRow circuit. This circuit is called pre-choose ShiftRow architecture. By way of combine pipeline with parallel architecture that provides high data throughput about 870Mbits/s and lower gate counts about 397369. In this thesis compared with parallel and pipeline architecture, the speed is higher 50% and the area is smaller 20%.