Synthesis of Bundled Data Asynchronous Circuits

• Main Authors: Jou-Chun Lin, 林柔君
• Other Authors: Fu-Chiung Cheng
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/05846171636999972725

碩士 === 大同大學 === 資訊工程學系(所) === 98 === Bundled data asynchronous circuits have the following advantages: low power consumption, low cost and low EMI (electromagnetic interference) compared to other types of circuits. To realize bundled data circuits, however, we must solve the following issues: first, how to add matched delays to the datapath latches or to fix timing violations (setup and hold time constraints) if edge-triggered flip flops are used. Second, how to deal with missing handshake components due to synchronous circuit optimization tool (such as Quartus). Third, how to design a parameterized handshake components to facilitate system design, debug and delay adjustment. In this thesis, we develop a CAD tool written in Java to synthesize Balsa Breeze circuits into debugable bundled data asynchronous circuits based on a set of parameterized handshake components. The circuits are tested and verified in Altera Quartus II 9.0 and a DE2 FPGA board. The experimental results show that our bundled data asynchronous circuits outperform dual-rail asynchronous and Altera C2H synchronous circuits in terms of circuit cost, power consumption and speed.