| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 98 === In this thesis, we proposed a novel parallel phase turbo decoding algorithm for VLSI architecture. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce a long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. Besides, we modify the received data RAM to reduce the decoding time. By using this method, the decoder can reduce half frame decoding latency.
To verify the function of the proposed parallel phase turbo decoder, we have used Xilinx Virtex-5 FPGA to emulate the hardware architectures, and we have designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. The gate counts of this decoder chip are 128284. The chip size including I/O pad is 1.91×1.91mm2, and power consumption is 151.76mW. The simulation results show that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.29% ~ 58.63% decoding time saved, with 8 iteration times at 100MHz working frequency.
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