Comprehensive Study of Signal Ordering Impacts on Digital Circuits

• Main Authors: An-Tai Tsai, 蔡安泰
• Other Authors: Jung-Lin Yang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/97461753769623176279

碩士 === 南台科技大學 === 電子工程系 === 98 === This thesis is not in an attempt to design a brand new logic circuit in order to improve the performance, instead, it provides readers a different methodology from the conventional way for circuit performance improvement. With long years of history on digital circuit design textbooks, we often read that "If there are multiple input signals, we shall connect the last input signal to the closest signal output". This description may be read simple and well known but most of VLSI textbooks stress on teaching readers the circuit design and synchronization principle, and the implication and explanation of the saying is often briefly discussed or omitted. Therefore, we take those words as the starting point of this thesis, and to further discuss and realize to verify the meaning behind the saying. The digital logic circuits mainly consist of combinational logic circuits and sequential circuits. And the way of implementation consist of synchronous and asynchronous circuits in terms of circuit realization, of which contain static logic circuits, dynamic logic circuits, and general-C element circuits and so on. We use TSMC 0.35um technology for the purpose of the implementation and analysis on CMOS circuit element, and to use the data obtained in the experiment to analysis and demonstrate the advantage of the designed circuit. In the operational principle of the synchronous circuit, the overall circuit clock cycle must be the worst-case clock as the clock cycle. Although the theory taught by the textbook is just to speed up the clock cycle on the worst-case element, it does not much good to the overall circuit performance. On the other hand, asynchronous is just the opposite. The asynchronous circuit uses handshaking to coordinate the operational clock time independently between two elements, and this way would be able to improve the performance of each circuit element used. If we sum the improvement up, we would notice that a great leap of improvement is being done. This thesis not merely demonstrates the analytic results and characteristics on few of the selected digital logic circuits, it also shows on how the analytic result and characteristics may vary and lead to different overall performance as we re-arrange signal ordering and location. Thus, this thesis intends to guide the readers on how to concisely analyze circuit property, then further to see the variation of the signal analysis and in the circuit re-location. Moreover, we designe an asynchronous circuit controller to demonstrate our experiment result, and hope readers would be benefited from it.