| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 98 === As the time advances, there are various electronic products available on the market. In order to make competitive products, designers have to constantly upgrade the equipment used and to increase the inventiveness of a product. Therefore, the key to a success relies on how well a new product is designed and how fast the new product is ready to market. It is said to be diversified in the similar electronic products that are found on the market today, and criterion such as high efficiency, low power, and EMI-resist are what the electronic industry focuses on. In the process of searching the way to improve and to provide a better solution, advantages such as low power consumption, modularity, no clock skew and low EMI are discovered to fulfill the needs of the industrial intents. Nevertheless, after years of researches in both academia and the industry on topic of asynchronous circuit design, the creation still cannot be widely used in application. The reasons are: current available design tools are mainly synchronous-based; and tools specified for the design of asynchronous circuits are rare. Plus, the design methodology of asynchronous circuit is highly complicated, and autonomous self-assist learner can hardly pick up the design concept with difficulties. Therefore, the applications of asynchronous circuit design are less likely to be accepted by the market.
Currently, most of circuit design engineers use HDL to help the development of the circuit design. Although HDL does not stress to be synchronous or asynchronous, most developers only try to understand the application of the design flow via HDL in the synchronous way instead of asynchronous way. This thesis intends to elaborate on how to proceed to asynchronous circuit design in the hand-shaking level. Moreover, the handshaking element library of the VHDL version proposed by Myers is taken reference to the function applied in Verilog, so that Verilog-favored circuit designers could use this element library for the circuit design. This thesis will benefit the engineers in the design industry and the academic researchers.
This thesis uses both hardware description languages such as the VHDL and the Verilog to describe the handshaking level digital system. Further, we use burst-mode (BM) and the extended burst-mode (XBM) to illustrate the advantages. This research aims at full-custom IC design and FPGA design. Successful prototypes consist of comparator, adder, RSA, encoder, decoder, and some self-timed circuit. Moreover, we could use these circuit elements to perform a behavior signal simulation test, and further extract the detailed timing information of asynchronous finite state machines (AFSMs) from those signals for error detection measured in the synthesized self-timed circuit; the result could be traced and identified on where the rule violations occurs within the fundamental modules of the AFSMs.
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