| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === A time-domain analog-to-digital converter (ADC) is proposed in this thesis. There are three major circuits in the ADC: voltage-to-time converter, time-to-digital converter (TDC) and digital circuit. All the important building blocks, such as sample-and-hold, comparator, TDC and digital calibration, will be discussed in detail.
To solve the capacitor and resistor mismatch caused by PVT variations, a successive approximation register (SAR) technology will be adopted for error calibration. Two supply voltages of 3V and 2.5V are utilized to achieve 12-bit resolution and 700kHz sampling frequency. The input voltage is sampled first and then converted to a pulse with width proportional to the sampled voltage. Finally, a TDC is used for output coding. The test chips were fabricated in a TSMC 0.18?慆 Mixed-Signal 1P6M CMOS process. The chip area is merely 0.233 mm2 excluding I/O pads.
|
|---|
