A Low-Voltage Continuous-Time Sigma-Delta Modulator Chip Design with DWA Technology

• Main Authors: Yan-cheng Lai, 賴彥誠
• Other Authors: Jhin-fang Huang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/53597492085247881807

碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === Recently, continuous-time (CT) ΣΔ modulators gain growing interest in wireless applications for their lower consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts. Sigma-delta modulation techniques have been widely used in broadband and high accuracy analog/mixed-signal IC applications, such as analog-to-digital data converters (ADCs), digital-to-analog data converters (DACs), frequency synthesis, and power amplification. In the situation of low-voltage design, the signal dynamic range and sampling frequency are restricted by the high switch resistance in the switched-capacitor (SC) circuits. Due to the bandwidth limitation of the integrators, it is difficult to achieve wideband with high resolution. Hence, continuous-time ΣΔ modulator can be used to solve these problems. For a multibit ΣΔ modulator, the performance is directly related to the linearity of the internal multibit DAC in the feedback path. Various dynamic element matching (DEM) techniques have been proposed to improve the nonlinearity of the internal DAC. In the modulator, the data weighted averaging (DWA) algorithm is employed and provide first-order noise shaping of the DAC element mismatches. On the other hand, Capacitor tuning circuit is utilized to overcome loop coefficient shifts due to process variations. In digital signal processing, the design and analysis of the decimation filter is discussed including the comb filter and the finite impulse response (FIR) filter. In this thesis, we design and implement a low voltage, continuous-time sigma delta modulator for broadband application. The modulator mainly contains active-RC integrator, DWA circuit, feedback DAC circuit, and 4-bits quantizer operation at 160MHz. The modulator dissipates 19.8 mW at 1.2 V supply voltage and is fabricated in the TSMC 0.18 um 1P6M CMOS technology. Measurement results show the modulator achieves 51 dB SNR, a peak 48 dB SNDR and 54dB dynamic range over a 10 MHz band at an over-sampling ratio of 8.