FPGA Implementation of ΔΣ Modulators in Fractional-N PLL

• Main Authors: Cheng-lun Wen, 溫政倫
• Other Authors: Jhin-Fang Huang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/29235907026820955180

碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === Fractional-N synthesizers have many advantages over their conventional counterparts, integer N synthesizers. These include, among others, high frequency resolution, fast channel switching speed, low in-band phase noise, less stringent phase noise requirement on the external VCOs, permitting direct digital modulation. One way of achieving non-integer multiplication of the reference frequency is through switching the division ration of the divider among different integers so that the “average” divider output cycle seen by the phase frequency detector is a non-integer multiple of the VCO period. However, the dithering of the rising edge of the divider output, as a result of witch action, could cause unacceptably high phase noise and sidebands within the loop bandwidth if a simple bit stream generator is employed. High order Delta-Sigma Modulators capable of shifting low frequency noise into high frequencies are required. The shifted low frequency noise will be subsequently filtered out by the low pass response of the loop. In this thesis, a digital pipelined third-order MASH Delta-Sigma Modulators (DSMs) is analyzed, designed and implemented on field programmable gate array (FPGA) customer board (Lyrtech). The fractional division causes spurious tones at fractional multiples of the reference frequency. The Delta-Sigma fractional-N architecture seems to be widely accepted the spurious problem as the best one. Xilinx, Matlab, Modemsim and SignaWAVE are software tools for design and implementation. The DSMs are successfully implemented by FPGA. Both simulated and measured results are presented and compared discussed.