| Summary: | 碩士 === 臺灣大學 === 電機工程學研究所 === 98 === In recent years, the voltage-mode multi-phase interleaved buck converter configuration has been used extensively in the voltage regulators for powering computer central processors (CPUs). The CPUs are often operated like a dynamic load with step load frequencies ranging from kilohertz to megahertz. The combination of converter interleaving operation and the dynamic load may cause serious problems with beat-frequency (the difference of switching frequency and load frequency) phase current oscillation. In a multi-phase configuration, a current-balancing control loop is usually employed to reduce excessive phase current imbalance regardless of a beat-frequency oscillations problem. The focus of the thesis is to investigate the effects of the current-balancing control on the beat-frequency oscillation in a voltage-mode two-phase interleaved buck converter.
In the thesis, the current-balancing control is modeled from the points of view of phase-current balancing and beat-frequency oscillations. The model for the current balancing aspect was obtained by the conventional average modeling method. From the model, a definition of the control loop gain Tcb was proposed and derived using a rather unconventional approach. Tcb information is useful for designing the current-balancing loop. The model for the beat-frequency oscillations aspect was obtained by using the combination of average model and multi-frequency model. A loop gain expression Tbeat was obtained, which is useful to predict the performance of beat-frequency oscillation. It turns out that the two loop gains, although different in physical meaning, share the same expression form. In other words, once the current-balancing loop compensation is designed, the suppression characteristic on the beat frequency oscillation is also fixed. Therefore, the compensation design of the current-balancing loop must take both aspects into considerations. Simulations and experimental results were given to verify the models.
The model presented in this thesis is useful for the designers to compensate the current-balancing loop. Future research directions were also pointed out in the thesis.
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