| Summary: | 博士 === 臺灣大學 === 電機工程學研究所 === 98 === Different kinds of phase-locked loops (PLL) have been developed for various applications since the design of the first PLL in 1932. In recent years, the all-digital phase-locked loop (ADPLL) has been broadly studied for System-on-Chip (SoC) applications, because many designs need to be integrated into one chip in the SoC environment. In a majority of cases, these designs need a reliable clock source to work. As there is no RLC component involved in the ADPLL design, the ADPLL offers the dual advantage of being easy to integrate and entailing very low hardware overhead. From this point of view, the ADPLL offers the advantages of not only reducing both the production and design cost, but can also be produced for market in a very short span of time.
In Chapter 3~5, the dissertation presents improved circuits for each module of the ADPLL. Some of these modules are an improvement on recent published research while some have been newly developed using the DSP algorithm. All these modules maintain low hardware overhead along with good performance. This thesis also presents a systematic methodology to construct the DCO circuit. The new design methodology achieves a very low design cycle time for various processes and design specifications. In recent years, double data rate (DDR) circuits have become the major design components of high-speed circuits. This thesis also describes the operation of an all-digital pulse width control loop (ADPWCL), to produce an output equal to 50% of the duty cycle of the ADPLL for such high-speed circuits. In addition, the loop bandwidth of the ADPLL is usually lower and typically less than 1/1000 of the reference clock to yield a low loop response. In Chapter 3, this thesis presents an adaptive loop filter to adjust the loop bandwidth from a 100x to a value of <1/1000 reference clock. This is because the adaptive loop filter has the ability to adjust its loop bandwidth dynamically using its phase error. The optimized algorithm and hardware demonstrate a more compact hardware requirement as compared to current research and enable a high tracking performance with respect to the input reference clock. Lastly, this thesis also presents a new frequency estimation algorithm, which demonstrates a 350% improvement on the lock-in time as compared to the current state of the art.
Using the new approaches, we have developed many circuits based on the hardware description language (HDL). The developed ADPLL designs are not only easy to integrate into the SoC chip but also can also easily be applied to various CMOS processes.
In summary, the new approaches presented in this dissertation improve the overall design and performance of the ADPLL. All the proposed designs have been verified using a highly portable chip-level design.
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