| Summary: | 博士 === 臺灣大學 === 電機工程學研究所 === 98 === H.264 is the latest video compression standard with the highest coding efficiency, and the Full-Search and All-Binary Integer Motion Estimation (FSIME and ABIME) algorithms are usually adopted for getting best performance and reducing hardware area, respectively. However, the chip-area still increases significantly since the video resolution grows rapidly. Thus the testability is becoming more and more important. Fortunately, there are a number of repeated modules in the H.264-IME block, thus the well-known Iterative-Logic-Array (ILA) architecture can be applied to test all the modules with constant number of test patterns. The most important condition for the ILA architecture is that the I/O function of each module should be bijective (reversible). However, most of the original designs do not have this property. In this paper, effective ILA design-for-testability schemes are proposed for both H.264-FSIME and H.264-ABIME blocks. The repeated modules are modified to be bijective and cascaded as the ILA architecture. Then each module can be fully tested by only testing the first module exhaustively. A simple built-in self-test circuit is also proposed. Moreover, the physical designs of the scan-chain and the proposed test schemes are synthesized with the UMC 0.18um technology. The total test time of the proposed method is only about 13.53% of that of scan-chain method with ATPG (Automatic Test Pattern Generation), and the hardware and delay-time overheads are still very low.
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