60-GHz Low Power ASK Transceiver Design and Linearization of Low Noise Amplifier

• Main Authors: Wei-Hung Chou, 周韋宏
• Other Authors: 黃天偉
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/05749601203772806928

碩士 === 臺灣大學 === 電信工程學研究所 === 98 === In this thesis, a 60-GHz ASK Transceiver and a low noise amplifier with built-in linearizer are developed. As the demands for wireless communication technology are growing rapidly in the recent years, the usage of lower frequency band has gradually saturated, and it forces the research of millimeter-wave circuit design to become a hot topic. Furthermore, the transmission data rate has also increased which implies the task of designing the wideband transceiver would be essential. The standard of IEEE 802.15.3c has defined 7-GHz bandwidth to fulfill the high-speed transmission of wireless personal network, which is capable to transmit the high definition video file wirelessly in the few seconds. To realize the transceiver on the mobile devices, power consumption and manufacturing cost are definitely the major concerns. Therefore, in the first part of thesis, we propose the transceiver using the ASK modulation technique which tally with the foregoing purpose of low power consumption and manufacturing cost. They are fabricated by 0.13 μm CMOS technology. The transmitter includes a distributed active transformer (DAT) power amplifier and an ASK modulator. The transmitter OP1dB is 10.8 dBm for 561 mW dc power consumption, and it is expected to transmit the data over 2 Gbps. The transceiver is composed of a ASK modulator, a ASK demodulator, a medium power amplifier, and a traveling-wave type switch. The OP1dB is measured to be -4.7 dBm under mere 154.8 mW power consumption, and the data rate around 3 Gbps is achievable through modulation and demodulation measurement. In the second part, we discuss the nonlinearity problem which may lead to higher bit-error rate (BER) especially with high spectral-efficiency modulation technique. After comparing the existing linearization techniques, we propose a 90nm CMOS technology 60-GHz low power low noise amplifier with modified derivative superposition technique. The linearizer is placed in parallel to the gain stage and has been demonstrated 8-dB IMD3 suppression and 5-dB IIP3 improvement from original -5 dBm to 0 dBm. The peak gain is 11.5 dB and the dc power consumption is 10.8 mW. Besides, noise figure (NF) is 5.3 dB at 60 GHz and ranges from 4.4 dB to 6.3 dB in the interested band.