| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 98 === In the pursuit of the miniaturization and multifunction, the integrated systems on one packaging has become a trend nowadays in the advanced packaging technologies of semiconductor industry. Among them, 3D IC packaging is one of the main structures which stacks the different chips vertically and interconnects the chips by through silicon via (TSV) structure.
To design the novel TSV structure systematically, we analyzed TSV’s high-frequency characteristic and proposed an equivalent circuit model of the TSV based on the transmission line model. In order to apply TSV in the high-speed digital circuits and systems-in-package design, we analyzed the TSV equivalent circuit model in the frequency domain to verify the tolerable noise margin in 3D IC structure. For the purpose of verifying the availability of the proposed circuit model, the simulation results were compared with the measured experiment data refer to those of published international papers. In addition, to reduce the non-ideal effects in a stacking multilayered TSV structure for the high-frequency transmission, a useful compensation method ws proposed, which needs only one first-order RC equalizer to compensate completely in the frequency-domain response and improve the signal integrity on the eye-diagram.
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