Interconnects & 3D Integration

• Main Authors: Chun-Chang Chen, 陳羣昌
• Other Authors: Yu-Hsuan Kuo
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/60353503496468208295

碩士 === 國立臺灣大學 === 電子工程學研究所 === 98 === Following the CMOS transistor scaling down tendency, the effect of resistance and capacitance delay plays a decisive role. With the coplanar device, the interconnections between circuit and circuit are, relatively, very enormous, and then the resistance and capacitance delay cuts down the velocity of device very well. For reducing the average wire length of block-to-block interconnects, the three dimensional integration is an important key technique. Three-dimensional integration provides benefits for power efficiency, bandwidth, latency operation, performance and etc. For realizing the three-dimensional integration, the circuit is stacked one by one. Generally, stacking includes wafer-to-wafer, and die-to-wafer. The interconnections between stratum and stratum are using vias. In this thesis, via is a leading role. The thesis is primarily divided into two parts：(1) interconnections, and (2) etching for vias. Firstly, we use MATLABS and HFSS to simulate RC delay and frequency response, respectively. For reducing the transmission loss, the pattern is designed for GSG measurement. Through the semiconductor fabrication, the length of 3cm interconnection is fabricated well. The bandwidth of 3cm interconnection is about 200 MHz. As a result of insertion loss, we take a discussion with different materials. The different materials are deposited on germanium substrate, and the bandwidth is up to 5 GHz. We find the silver has the more excellent transmittance. In the second part, via is etched by inductive coupling plasma (ICP). And the aluminum is deposited in the lateral and bottom of vias. Through image of scanning electron microscope, we can see the cross-section of via. A lot of cross-section SEM is using to analyze vias. The dimension of vias are 10 μm × 10 μm, 20 μm × 20 μm, and 50 μm × 50 μm. The deepest via is up to 100 μm. In the 3D viewpoint, stacking is a useful method. Though planar interconnection and via, we can realize the three-dimensional integration. The functions of a chip are more and more various, and the systems on chip (SOC) can be arrived.