Noise Decoupling System and Low Noise Amplifier

• Main Authors: Cheng-Hung Li, 李政鴻
• Other Authors: Yi-Chang Lu
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/57013953093420825203

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === Noise usually causes signal distortion, thus degrading the circuit performance. In this thesis we discuss various sources of noise and the models of the substrate and power line at first. Then, a noise decoupling circuit is implemented using the PSC (Powerchip Semiconductor Corp.) high voltage process. The circuit has noise select, noise sources and the noise decoupling system. There are two types of experiments. First, on-chip noise sources are used to generate the internal noise. The magnitude of the substrate noise and power noise are measured with the noise decoupling system activated or deactivated. Then an external noise is applied through bias-T to observe the efficiency of noise suppression. There is about 40% reduction of noise. Secondly, a 5.8G low noise amplifier with an active inductor and noise decoupling system is implemented using 0.35um CMOS process. An active inductor is adopted to reduce chip area and costs. As to noise decoupling, it could reduce the noise figure of the LNA, so the circuit has better performance. The LNA exhibits input matching less than -11 dB, output matching less than -11 dB, 18 dB gain, 2.8 dB noise figure, -4 dBm IIP3, and 25 mW power consumption. Finally, an 8-12 GHz X-band broadband amplifier is implemented using 90 nm CMOS process. On-chip probing is used to measure the performance of the LNA. A shunt-feedback resistor and noise cancellation method are used in the amplifier designed to lower the noise figure. The LNA exhibits input matching less than -10 dB, output matching is less than -10 dB, 11dB gain, 2.5~4 dB noise figure, -7 dBm IIP3, and 8 mW power consumption.