The Design of Nanometer CMOS Pipelined A/D Converter

• Main Authors: Yen-Chuan Huang, 黃彥筌
• Other Authors: Tai-Cheng Lee
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/17806716844048339768

博士 === 臺灣大學 === 電子工程學研究所 === 98 === Analog-to-digital (A/D) converters which provide the link between the analog world and digital domain represent important building blocks in many systems. In this dissertation, three ADCs are presented to achieve small-area and low-power design objectives with analog approaches. First, a 9-bit cyclic ADC employs a novel multiply-by-two circuit for enhancing the speed of residue evaluation is presented. The residue evaluation and sampling phases are merged to reduce the conversion latency. Hence, only four clock cycles are required to perform a 9-bit conversion. The proposed 0.02-mm2 ADC has been fabricated in 90-nm digital CMOS technology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB with a core power consumption of 6.9 mW from a 1.0-V supply. Then, a 10-bit pipelined ADC employs both opamp and time sharing techniques to reduce the power consumption and silicon area is proposed. This ADC needs only one opamp to complete the 10-bit conversion. The prototype design also has been fabricated in 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the core power consumption is 4.5 mW from a 1.0-V supply. The last work was an extension of the second design. The conversion rate is efficiently boosted by four ADCs in parallel. The measured results give an SNDR of 53.0 dB and power consumption of 36 mW at a sampling rate of 400 MHz.