Using Multi-Bit Flip-Flops for Clock Power Saving

• Main Authors: Jung-Hung Weng, 翁榮鴻
• Other Authors: 郭斯彥
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/61030453492768584096

碩士 === 臺灣大學 === 電子工程學研究所 === 98 === In the recent years, low-power circuit design has become the most concerned issue in today’s design problems due to the popularity of the portable devices. From the previous design experience, the clock tree is one of the most power consumption components of the whole design. Reducing the power consumption of the clock tree can effectively reduce the overall power consumption. Therefore, many techniques on low-power clock tree design have been proposed. In addition, with increasingly sophisticated manufacturing process, the smallest inverter usually can drive more than a 1-bit flip-flop. Therefore, several 1-bit flip-flops can share the same drive, that is, the multi-bit flip-flops. It will effectively reduce the use of inverter, thereby reducing the overall power consumption and chip area. On the other hand, it can also effectively reduce the clock tree wire length, and thus also reduce the clock tree power consumption. The algorithm in this work can effectively reduce the total power of the designs. The power saving includes the flip-flops power saving, about 23%, and clock tree power saving, about 48%. On the other hand, merging 2,000,000 flip-flops with this algorithm can be achieved in least than 1 hour. The empirical time complexity of the algorithm is Θ(n1.052) which is less than the empirical time complexity of Θ(nlogn) time complexity algorithm.