Decoding BCH Codes Based on Welch-Berlekamp Algorithm

• Main Authors: Tso Shen, 沈佐
• Other Authors: Hung-Ta Pai
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/89565220111144361743

碩士 === 國立臺北大學 === 通訊工程研究所 === 98 === Due to concepts of multi-level cell (MLC), disturbance and data retention of flash memories have become critical issues in recent years. Error Correction Codes (ECC) have been suggested to correct errors during memory reading to increase the reliability of the memory.One of them is the BCH code. Because there are already existing designs for BCH encoder and Chien search, we focus on the key equation calculation. There are three algorithms that can be used to solve the key equation calculation: Euclid, Berlekamp-Massey(BM), and Welch Berlekamp (WB) algorithms. Our research in this thesis propose the WB algorithm hardware design of the BCH code. 　　 The WB algorithm calculates remainders instead of syndromes so that its complexity can be decreased. However, it is necessary to update four polynomials at each iteration. The update needs many logic gates. We propose a method to reduce the gate count. 　　 In this study, we design a (8560,8224) BCH code with 24-bit correction capability. The parallel architecture is used in the remainder calculation block, so that it can decrease system’s clock cycles. We simulate the code using NCverilog and Debussy, get a synthesis report by Xilinx ISE, and verify it on Xilinx Virtex4 FPGA.