Column Level Binning of CMOS Image Sensor for Low-Light Imaging
碩士 === 國立臺北大學 === 電機工程研究所 === 98 === This work presents a column level binning circuit for a CMOS image sensor for the purpose of low-light imaging. A 2 x 2 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1/4 of the original size and every two columns o...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/40376475932037728638 |
| Summary: | 碩士 === 國立臺北大學 === 電機工程研究所 === 98 === This work presents a column level binning circuit for a CMOS image sensor for the purpose of low-light imaging. A 2 x 2 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1/4 of the original size and every two columns of the pixel array share one binning circuit. The output signal of each pixel is sampled unto the binning circuit basically composed of two adjacent correlated double sampling circuit averaged by means of a row average switch. A 0.18μm TSMC process was used to simulate the circuit and simulation results reveal a kernel averaging error of less than or equal to 2% for low-light conditions with a power consumption of 123.9μW.
The ADC was designed using a single-slope A/D conversion topology with a simple circuit structure to effectively reduce area and power consumption. The designed ADC was compatible for both non-binning mode and binning mode. It has a correlated double sampling stage to eliminate fixed-pattern noise and extract the photoelectric data by subtracting the reset and signal values from the pixel or the averaged signal values from binning circuit. FFT simulation results reveal an ENOB of 7.3 bits for typical condition (TT, 55oC), a power consumption of 128.5μW per column ADC array and a power consumption of 258.4μW for the binning circuit and its output incorporated with two column ADCs. The frame rate for the CMOS image sensor is 84 fps.
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