A Fast Single Slope ADC with Vernier Delay Line Technique

• Main Authors: Lin, Wei-fong, 林蔚峰
• Other Authors: Chou, Hwai-pwu
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/40521255472338151280

碩士 === 國立清華大學 === 工程與系統科學系 === 98 === Integrating type analog-to-digital converter (ADC) is commonly used for nuclear radiation spectrometers for pulse height measurement. Vernier delay line (VDL) techniques have been proposed for time measurement and can reduce conversion time significantly. With improving time resolution of VDLs, the timing error due to comparator delays and the non-linearity of ramp generator become a concern for improving the performance of the single slope ADC. The present work is to use a two-level VDL for high resolution timing measurement and to develop an amplitude-to-time converter with high precision to reduce timing errors in the time conversion process. A 9-bit single slope ADC is realized with the process of TSMC CMOS 0.18um 1P6M. Its sample rate is 5Msps. And the minimum time resolution is about 150ps, the DNL is within -0.4~+0.5 LSB, and the INL is within -0.1~1.1 LSB.