| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 98 === This thesis reports the design and implementation of a time-to-digital convertor (TDC) with high resolution, wide detect range, and low power dissipation. Conventionally, the time resolution of a conventional delay-line based TDC is usually limited by the delay cell. Recently, several TDC structures have been proposed to provide sub-gate-delay resolutions, such as Vernier delay line, passive time interpolation, and time residue amplification. However, the finer resolution makes the number of delay elements grow fast.
This work describes a counter-based high-resolution TDC with a multi-path ring oscillator (MRO) as the timing generator. Precise conversion of sub-gate-delay resolution is based on a pair of counters and state-to-phase (S2P) logics. The MRO is optimized with an improved timing model and power consumption analysis. Running from a single 1.2-V power supply, experimental results for the TDC prototype show that less than 6 ps resolution is achieved with 9.6mW power consumption. The TDC has been fabricated in a tandard 90-nm CMOS process. The die area is 0.18 mm2.
|
|---|
