| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 98 === Dynamic voltage scheduling (DVS) technique is an effective solution to manage the power for performance-power optimization in portable electronic devices. In this thesis, a monolithic ultra-fast current-mode adaptive on-time buck converter for DVS applications is presented firstly. The proposed technique can dynamically adjust the turn-on time of power switches according to the changes of input voltage and output voltage in steady-state operation and can change switching cycles instantaneously in transient operation. With the proposed control scheme, the dc-dc converters can accomplish both fast transient response and the capability of mitigating the switching-frequency variation. Experimental results show that the proposed converter can keep the switching-frequency constant at 650 kHz to within +-5% over the entire operation range. With a load resistor of 10 Ω, the reference tracking speeds are 11.3 μs/V for a 1.5 V step-up output change and 13.3 μs/V for a 1.5V step-down output change, respectively. The recovery times for a step load change between 50 mA to 500 mA are less than 15 μs. The transient performance is faster than the exiting counterparts.
Linear low drop-out (LDO) regulator is another fundamental block of the power management circuit. The stability of the LDO is the most significant concern. Thus, an active frequency compensation circuit for low dropout regulators (LDOs) is presented in the second part. Compared with the conventional compensation scheme, the proposed circuit can greatly boost the effective current multiplication factor by at least one order of magnitude without increasing any power consumption. The proposed circuit can generate an internal lower frequency zero and push parasitic poles toward extremely high frequency such that the loop bandwidth can be extended drastically. The required on-chip capacitance is reduced to 0.4 pF, comparing to 5 pF in the conventional compensation scheme. Implemented in a 0.35-μm 2P4M CMOS process, the LDO with the proposed active frequency compensation circuit consumes 27 μA ground current at 150 mA maximum output current with a dropout voltage of 200 mV. Experimental results show that the proposed LDO structure has achieved only 10% settling time of the conventional compensation scheme.
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