| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 98 === In recent years, power has become one of the most important issues for chip designs. A lot of low-power design techniques have been developed. In digital circuits, adaptive voltage scaling is an effective approach to achieve low power design due to its lower supply voltage. This thesis focuses on the digital circuit operation while the power supply voltage is scaled down even to the sub-threshold region of the MOS transistor. The issues we encountered may happen not only in low power design but also become common issues while the supply voltage scaling down to close the threshold voltage in advanced technologies.
With different (lower) supply voltage, the characteristic of circuit would be changed significantly. The design guidelines in nominal supply voltage cannot guarantee optimumality in low supply voltage. We are going to fix the performance degradation due to threshold voltage mismatch of PMOS and NMOS when voltage is scaled down. Develop a feasible solution to design a voltage insensitive digital circuit. It can be used in DVFS (Dynamic Voltage Frequency Scaling) system. Then we check the functionality of common used cell in digital circuits such as sequential cells, transmission gates, and other logic cells. Moreover, we’ll take a look at the circuit architecture to ensure the circuit not to deviate the optimal point too far.
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