A Short-Channel Variable Gain Amplifier with DC Offset Cancellation and Gain Calibration Loop

• Main Authors: Yang, Hui-Chen, 楊蕙甄
• Other Authors: Hsieh, Chih-Cheng
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/63026791132656734491

碩士 === 國立清華大學 === 電機工程學系 === 98 === In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration. The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations. An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.