A High-speed and Low-power Continuous-time Sigma-delta Modulator in 0.35-μm CMOS Technology

• Main Authors: Sie, Jhih-Yuan, 解智淵
• Other Authors: Hsu, Klaus Yung-Jane
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/94823727875452206043

碩士 === 國立清華大學 === 電子工程研究所 === 98 === A high-speed and low-power continuous-time sigma-delta modulator(CTSDM) is implemented in standard TSMC 0.35-μm CMOS 2P4M technology. The CTSDM is targeted for applications which demand wide-bandwidth, medium-resolution and low-power such as wireless communication, imaging or digital video. The CTSDM comprises a third-order RC-integrator loop filter, a 4-bit current steering digital-to- analog converter, and a 4-bit flash analog-to-digital converter operating at 200-MHz clock frequency. The noise-shaping design is determined using modified Z-transform between discrete-time and continuous-time coefficients of the loop filter transfer function. The excess loop delay is set to half sampling period and the degradation of modulator stability due to excess loop delay is avoided with a negative path feedback and 4-bit trimming circuit. The CTSDM achieves 65.5-dB DR, and a 64.5-dB SNDR or 10.5 ENOB over a 10-MHz input bandwidth at 10 times oversampling rate. The total power consumption is only 20.2-mW from the 3-V power supply, and the core area is 1.4X1.1-mm^2.