Estimating the influence of substrate noise on a SAR ADC in pre-layout simulation

• Main Authors: Fan, Yang-Hang, 范揚航
• Other Authors: Chen, Hsin
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/71454648146569729916

碩士 === 國立清華大學 === 電子工程研究所 === 98 === Analog and digital circuits are combined on the same substrate of the bio-chip. Noise propagating through the substrate influences analog circuit performances. It is difficult to understand this phenomenon before layout extraction because the technology file which is used to simulate circuits does not include the substrate information. In this thesis, a method to measure the substrate information is designed, and a substrate resistance formula based on the measured substrate information is built. A substrate resistive network is built using the substrate resistance formula according the layout, and the network is added between the noise input and analog circuit for pre-layout simulation to compensate the lack of the technology file. Once the network is built, simulation results of the circuit with the substrate resistive network before layout extraction are compared to the chip measurement results to study how valid the substrate resistive network is because it is exceedingly difficult to build the perfect substrate resistive network. The Successive Approxi- mation Register Analog to Digital converter (SAR A/D) is used to test the accuracy of the substrate resistance network because SAR A/D is widely applied to bio-chips and complete analysis methods of the SAR A/D such as SNDR and ENOB are available This thesis’s feature is testing substrate resistive network with the SAR A/D which is different from the testing circuits of references. Using the SNDR and ENOB analysis to quantize circuit variations caused by the noise interference for circuit pre-layout simulation and chip measurement can exactly describe the effect of signal interference. Various types of signals that interfere with the Sample and Hold (S/H) circuit of the SAR A/D are injected into the substrate near the S/H circuit for pre-layout simulation and chip measurement to investigate whether the substrate resistive network accurately represents the substrate coupling paths.