Design and Implementation of A Personal Gateway for Body Area Networks

• Main Authors: Chi-Chung Huang, 黃祺峻
• Other Authors: Chua-Chin Wang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/02480137669571168377

博士 === 國立中山大學 === 電機工程學系研究所 === 98 === In this thesis, we propose a personal gateway for wireless body area network(WBAN). By using wireless communication and a proper WBAN topology, patients’ physiological signal could be recorded without restricting their mobility. Moreover, integration of several kinds of signals from different sensor nodes in one data platform, personal gateway (PG), can reduce the redundant hardware of individual links as well as the complexity of WBAN. A device for long-term bladder urine pressure measurement is designed as a sensor node of PG. Not only is the design cost reduced, but also the reliability is enhanced by using a 1-atm canceling sensing IA (instrumentation amplifier). Because the urine pressure inside the bladder does not vary drastically, both the sleeping and working modes are required to save the battery power for the long-term observation. To integrate circuits with different supply voltages in PG, a 0.9/1.2/1.8/2.5/3.3/5.0 V wide-range I/O buffer carried out using a typical CMOS process is designed. An input buffer with a logic calibration circuit is used for receiving a low voltage signal. A novel floating N-well circuit is employed to remove the body effect at the output PMOS. Moreover, a dynamic driving detector is included to equalize the turn-on voltages for the output PMOS and NMOS transistors. ZigBee is used as a communication channel in this thesis because of its features, including low power, low complexity, medium range, and medium data rate. The 868/915 MHz mode has lower cost and power consumption than those of 2.4 GHz mode, and the data rate is far enough for WBAN applications. Moreover, lower carrier frequency causes less unnecessary power absorbed by human tissue. Therefore, the ZigBee tranceiver with 868/915 MHz mode is explored. A low power all digital phase lock loop (ADPLL) using a controller which employs a binary frequency searching method is also proposed as a clock generator of PG. Glitch hazards and timing violations which occurred very often in prior ADPLLs are avoided by a novel control method and a new digital-controlled oscillator (DCO) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically.