Compiler/Hardware Codesign and Memory Management for a Novel 3D Graphics Processor

• Main Authors: Sheng-Chih Tseng, 曾聖智
• Other Authors: Steve W. Haga
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/75429567281236386798

碩士 === 國立中山大學 === 資訊工程學系研究所 === 98 === This thesis is part of a large, multi-laboratory project to develop a GPU system-on-chip (SoC) for embedded systems. In support of this project, this current thesis presents the assembler and linker for the overall system. These tools were developed “from scratch” for this project, because the both the input (to our assembler) and the output (from our linker) have new formats, due to the novelty of our GPU. One of the challenges of the work in this thesis is the problem of memory management. Another is the problem of deciding upon an assembly format. But the largest challenge was in co-design. The assembler has to work with a compiler which is also under development by other students. Also, the machine instructions that we produce have to support the format and functionality of the GPU hardware. To accomplish this, the specific details of this hardware had to be rigorously defined through discussion and negotiation. Furthermore, the memory addresses also required codesign with the benchmark development team, which needs to have access to these memory locations. So codesign issues impacted many of the features of this thesis.