Design, Analysis and Applications of Hybrid CORDIC Processor Architectures

• Main Authors: Cheng-Han Lee, 李承翰
• Other Authors: Shen-Fu Hsiao
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/30754590303532389406

碩士 === 國立中山大學 === 資訊工程學系研究所 === 98 === In this thesis, we propose different CORDIC architectures which solve the problems of long-latency in traditional pipeline CORDIC and the large-area cost in table-based CORDIC. The original table-based CORDIC can be divided into two stages, coarse stage and fine stage. We also propose the three-stage architectures, composed of traditional pipeline CORDIC, Rom/Multiplier architecture and linear approximation. Detailed analysis and estimation in area and latency of these different two-stage and three-stage architectures with different bit accuracy are given in order to determine the best architecture design for a particular precision. Finally, we choose one of the architectures to implement, compare the results, and show its applications.