Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications

碩士 === 國立中山大學 === 資訊工程學系研究所 === 98 === In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The...

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Main Authors: Cang-yuan Guo, 郭倉源
Other Authors: Shiann-Rong Kuang
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/72910157957846921579
id ndltd-TW-098NSYS5392012
record_format oai_dc
spelling ndltd-TW-098NSYS53920122015-10-13T18:35:39Z http://ndltd.ncl.edu.tw/handle/72910157957846921579 Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications 適用於多媒體應用的低功率多重精確度重複式浮點乘器 Cang-yuan Guo 郭倉源 碩士 國立中山大學 資訊工程學系研究所 98 In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion Shiann-Rong Kuang 鄺獻榮 2010 學位論文 ; thesis 80 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立中山大學 === 資訊工程學系研究所 === 98 === In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion
author2 Shiann-Rong Kuang
author_facet Shiann-Rong Kuang
Cang-yuan Guo
郭倉源
author Cang-yuan Guo
郭倉源
spellingShingle Cang-yuan Guo
郭倉源
Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
author_sort Cang-yuan Guo
title Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
title_short Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
title_full Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
title_fullStr Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
title_full_unstemmed Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications
title_sort multiple precision iterative floating-point multiplier for low-power applications
publishDate 2010
url http://ndltd.ncl.edu.tw/handle/72910157957846921579
work_keys_str_mv AT cangyuanguo multipleprecisioniterativefloatingpointmultiplierforlowpowerapplications
AT guōcāngyuán multipleprecisioniterativefloatingpointmultiplierforlowpowerapplications
AT cangyuanguo shìyòngyúduōméitǐyīngyòngdedīgōnglǜduōzhòngjīngquèdùzhòngfùshìfúdiǎnchéngqì
AT guōcāngyuán shìyòngyúduōméitǐyīngyòngdedīgōnglǜduōzhòngjīngquèdùzhòngfùshìfúdiǎnchéngqì
_version_ 1718035621436456960