| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 98 === This thesis presents a design on basic two-stage operational amplifier with Taiwan Semiconductor Manufacturing Company (TSMC) offer library of TSMC 0.18um 1P6M+, 1.8V/3.3V (1- Polysilicon 6-Metal+) and 0.35um 2P4M，3.3V/5V (2-Polysilicon 4-Metal).
The key points are focusing on open-loop gain, unit gain frequency and total consumption power. We apply short channel length effect to extend open-loop gain and unit gain frequency with low power consumption. For design a CMOS two-stage operational amplifier, the original circuit makes the open-loop gain is about 70dB and the unit gain frequency is greater than 10 MHz. We designed a circuit with open-loop gain greater than 70dB and unit gain frequency greater than hundreds MHz. The unit gain frequency is extended to 450 MHz, the open loop gain is improved to 78dB.
The design skill is to utilize a cascaded structure and connect single capacitor to make negative feedback circuit for the marginal compensation of the frequency and phase margin. The phase margin is greater than 60o, therefore the circuit did not distortion. However, the relative output impedance will be reduced from 100-200K ohm to60 K ohm. The total power consumption is 0.13mW and the current consumption is 93mA. In addition, the advantage of our CMOS amplifier is extending the unit gain frequency and open-loop gain does drop. The total consumption power is less than 1 mW.
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