| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 98 === The development of modern electronic and communication, this architecture of frequency synthesizer has been used in many applications, such as frequency generator, clock recovery, clock synchronization and spread spectrum communication systems. Conventionally, the frequency synthesizer based on phase locked loop (PLL) that generation same frequency but different phases by multi-phase voltage control oscillator. Flying-adder frequency synthesis architecture is a novel technique to generation clock synchronization by concept of time-average frequency. Its basic architecture includes one multiphase PLL and one flying-adder. Flying-Adder can change frequency quickly by frequency control bit (FREQ). Furthermore, using fractional part of FREQ can get higher resolution for output frequency. However, the flying-adder frequency synthesizer will be affected by fractional spurs, causing the output frequency with serious jitter.
This paper presents an interpolated flying-adder frequency synthesis architecture. We also perform the theoretical jitter analysis by means of an interpolated multiplexer. The interpolated multiplexer includes a multiplexer and an interpolator to interpolate the signals that reduces the jitter. In addition, we design a multiphase digital phase locked loop to generate the 32 phase outputs. The chip area of a multiphase digital locked loop has been reduced. The chip has been implemented in TSMC 0.18um. The core area of the chip is 529.33 * 408.27um² and the total area is 1063 * 1063um² including 28 ESD pins.
The manufactured chip includes a multiphase digital phase locked loop, a flying-adder frequency synthesizer and one interpolated flying-adder frequency synthesizer. The multiphase digital phase locked loop generates the 32 phase outputs for flying-adder frequency synthesizer as well as interpolated flying-adder frequency synthesizer. The peak-to-peak jitter is 881ps and RMS jitter is 147ps when flying-adder frequency synthesizer’s output frequency is 174.6MHz. When interpolated flying-adder frequency synthesizer’s output frequency is 57.66MHz, the peak-to-peak jitter is 1.29ns and RMS jitter is 216.3ps.
|
|---|
