Algorithm and Architecture Design of Real-Time Adaptive Rate Control in H.264/AVC Video System

• Main Authors: Szu-Hong Wang, 王斯弘
• Other Authors: Shih-Chang Hsia
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/16529007995163739609

博士 === 國立高雄第一科技大學 === 工程科技研究所 === 98 === Rate control is a key technique for video compression and transmission because it regulates the bitrate throughput of a video encoder in order to obtain optimum visual quality under the channel bandwidth constraint and to avoid buffer overflow or underflow. For H.264/AVC, the reference rate control mechanism of JVT-G012 [32] uses a linear mean absolute difference (MAD) prediction model to predict the MAD of the current basic unit in the frame and a quadratic rate-distortion (Q2 R-D) model to calculate the quantization parameter (QP). However, the linear regression method employed to update the parameters of the linear MAD prediction model and Q2 R-D model is not suitable unfavorable for hardware implementation. In this dissertation, a low-complexity rate control algorithm is presented for the H.264/AVC encoder. The algorithm using spatio-temporal information can effectively improve video quality. This dissertation has three major contributions. Firstly, an adaptive group-of-picture (AGOP) rate control algorithm is proposed to improve the coding performance of the H.264/AVC system. The algorithm evaluates the temporal correlation between inter-frames to determine whether the AGOP structure should be used, and dynamically adjusts the QP using feedback information to improve video quality. Secondly, the defects of JVT-G012 [32] are analyzed to develop an adaptive rate control algorithm for real-time H.264/AVC encoder. The algorithm includes four major parts: 1) the initial QP decision based on the Laplacian of Gaussian operator, 2) the macroblock-level quantization parameter calculated based on the spatio-temporal correlation, 3) the adaptive GOP structure scheme, and 4) the appropriate quantization parameter re-calculated in scene case. Finally, the proposed adaptive rate control algorithm is realized with module-by-module for real-time applications. The VLSI chip is prototyped with 26K gates and implemented with 0.18-μm TSMC CMOS technology. The power consume is about 3.68 mW of when operation frequency is at 129 MHz.