Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter

碩士 === 國立東華大學 === 電機工程學系 === 98 === In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade boot...

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Main Authors:	Hsiao-Cheng Chiang, 蔣孝呈
Other Authors:	Ro-Min Weng
Format:	Others
Language:	zh-TW
Published:	2010
Online Access:	http://ndltd.ncl.edu.tw/handle/92235482442958605901

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spelling	ndltd-TW-098NDHU54420482016-04-22T04:23:11Z http://ndltd.ncl.edu.tw/handle/92235482442958605901 Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter 10位元50MS/s取樣頻率之管線式類比至數位轉換器設計 Hsiao-Cheng Chiang 蔣孝呈碩士國立東華大學電機工程學系 98 In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade bootstrap switch is better than that of the traditional one. The 10-bit pipelined ADC architecture includes nine stages. A 1.5-bit/per stage and a 2-bit flash ADC are adopted in the last stage. To reduce the power consumption, the front-end sample and hold circuit is removed. The opamp sharing techniques are used in the first to eighth stage. Pipelined ADCs use fully differential architecture to reduce common mode noise interference. The designed ADCs are simulated by HSPICE using TSMC 0.35 Ro-Min Weng 翁若敏 2010 學位論文 ; thesis 82 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立東華大學 === 電機工程學系 === 98 === In this thesis, 10-bit 50MS/s pipelined analog-to-digital converters (ADCs) are designed. The supply voltage is 3.3V. To improve the linearity of ADCs, a cascade bootstrap switch is proposed. The dynamic performance of the 10-bit pipelined ADC with a cascade bootstrap switch is better than that of the traditional one. The 10-bit pipelined ADC architecture includes nine stages. A 1.5-bit/per stage and a 2-bit flash ADC are adopted in the last stage. To reduce the power consumption, the front-end sample and hold circuit is removed. The opamp sharing techniques are used in the first to eighth stage. Pipelined ADCs use fully differential architecture to reduce common mode noise interference. The designed ADCs are simulated by HSPICE using TSMC 0.35
author2	Ro-Min Weng
author_facet	Ro-Min Weng Hsiao-Cheng Chiang 蔣孝呈
author	Hsiao-Cheng Chiang 蔣孝呈
spellingShingle	Hsiao-Cheng Chiang 蔣孝呈 Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
author_sort	Hsiao-Cheng Chiang
title	Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
title_short	Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
title_full	Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
title_fullStr	Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
title_full_unstemmed	Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter
title_sort	design of 10-bit 50ms/s pipelined analog-to-digital converter
publishDate	2010
url	http://ndltd.ncl.edu.tw/handle/92235482442958605901
work_keys_str_mv	AT hsiaochengchiang designof10bit50msspipelinedanalogtodigitalconverter AT jiǎngxiàochéng designof10bit50msspipelinedanalogtodigitalconverter AT hsiaochengchiang 10wèiyuán50mssqǔyàngpínlǜzhīguǎnxiànshìlèibǐzhìshùwèizhuǎnhuànqìshèjì AT jiǎngxiàochéng 10wèiyuán50mssqǔyàngpínlǜzhīguǎnxiànshìlèibǐzhìshùwèizhuǎnhuànqìshèjì
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Design of 10-bit 50MS/s Pipelined Analog-to-Digital Converter

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