| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 98 === Since, the portable digital image products are popular in recent years, the circuit are needed to extend the battery life. A cyclic low power analog-to-digital converter is usually used in the system of portable produces, like image sensor systems, digital cameras, etc. The most characteristic of the structure is low power consumption which can increase the working time. In this paper, a cyclic analog-to-digital converter (ADC) and a flash analog-to-digital converter are presented.
There are two parts in cyclic ADC. The analog part includes two operational amplifiers, four capacitors, and ten clock switches. The cyclic clock is utilized to generate digital code. The operational amplifiers can be reused from these digital codes. For this reason, the power consumption and the chip area can be decreased. The digital part includes the D flip-flops and multiplexers. A cyclic ADC is realized by the switching capacitors and voltage compared by the operational amplifier. The differences of a cyclic ADC and a traditional ADC are that a cyclic ADC only includes two operational amplifiers and the traditional ADC composed of many operational amplifiers. Because of using only two operational amplifiers, the advantage of a cyclic ADC is low power consumption and the small chip area.
The flash ADC includes sixteen resisters and fifteen comparators and digital logic gates. By using resistor divider, comparators compared with the reference voltage and coding circuits generate digital signals, thus the speed can be increase. A flash ADC is realized by the resister divider and the parallel processing signal. Because more comparators and resisters are required, the power consumption and the chip area will be increased.
The realized ADCs are presented and simulated by Hspice. The 8-bits cyclic ADC use TSMC 0.18um CMOS standard process. The supply voltage is 1.8V and the input voltage range is form -0.5V to 0.5V. The 4-bits flash ADC is simulated at 3.3 supply voltage by TSMC 0.35um CMOS standard process. The input signal range is 0.5~0.25V. DNL and INL are -0.1~+0.1LSB and 0~+0.4LSB, respectively. The power consumption is 234uW.
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