| Summary: | 碩士 === 國立東華大學 === 電子工程研究所 === 98 === The RC6 algorithm is an effective encryption method proposed in recent years. It is a type of symmetric-key encryption, which not only provides enough data security but also supports simple 128-bit block cipher encryption. The key feature of the RC6 algorithm is that it uses large amount of data dependencies in its computation. This feature facilitates relatively less computation during the rotate operation stage in the core of the algorithm, while it still meets the data security requirements. Furthermore, the RC6 algorithm flexibly supports 128-bit, 192-bit and 256-bit key length.
In this thesis, we present the efficient design of the RC6 cipher for encryption and decryption sharing the same hardware. Based on the analysis of the characteristics of the RC6 algorithm, we parallelize the operations of the independent data and use the same components. Furthermore, the design can be used for either encryption or decryption with limited hardware complexity. During runtime, it can generate the ciphertext from the plaintext or vice versa by controlling the data flow dynamically.
We have implemented the VLSI design of the RC6 algorithm. The combinational circuits area can be saved for approximately 21% compared with the design using separate encryption and decryption hardware modules. The portion without combinational circuitry can be saved for approximately 50%. The whole circuitry can be saved for approximately 24% including both parts in the above.
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